1. Field of the Invention
The present invention relates to a multi-level type nonvolatile semiconductor memory device for recording trinary or more data in a memory cell and to a method of data programming the same.
2. Description of the Related Art
A nonvolatile semiconductor memory device such as a flash memory normally has a binary type memory cell structure for recording data taking two values of "0" and "1" in one memory transistor.
Along with the recent demands for increasing the capacity of semiconductor memory devices, a so-called multi-level type nonvolatile semiconductor memory device for recording trinary or more data in one memory cell transistor has been proposed (refer to for example "A Multi-Level 32 Mb Flash Memory" '95 ISSCC P132 on).
FIG. 1 is a view of the relationship between a threshold voltage Vth level and data content where a data consisting of 2 bits and taking four values is recorded in one memory transistor in a NAND type flash memory.
In FIG. 1, an ordinate represents the threshold voltage Vth of the memory transistor, and an abscissa represents a frequency of distribution of the memory transistor.
Further, the content of the 2-bit data comprising the data recorded in one memory transistor is represented by [IO.sub.n+1, IO.sub.n ]. Four states of [IO.sub.n+1, IO.sub.n ]=[1, 1], [1, 0], [0, 1], and [0, 0] exist. Namely, four states of data "0", data "1", data "2". and data "3" exist.
A NAND type flash memory for writing multi-level data in units of pages (units of word lines) has been proposed (refer to for example the document: 1996 IEEE International Solid-State Circuits Conference, ISSCC96/SESSION 2/FLASH MEMORY/PAPER TP 2.1:A 3.3 V 128 Mb Multi-Level NAND Flash Memory for Mass Storage Application, pp 32-33).
FIG. 2 is a circuit diagram of the structure of principal parts of a NAND type flash memory for performing a write operation in units of pages disclosed in the above document.
In FIG. 2, 1 denotes a memory cell array, 2 a write/read control circuit, and BL1 and BL2 denote bit lines.
The memory cell array 1 is constituted by memory strings A0 and A1 having memory cells which are connected to common word lines WL0 to WL15. The memory string A0 is connected to the bit line BL1, and the memory string A1 is connected to the bit line BL2.
The memory string A0 has a NAND string in which memory cell transistors MT0A to MT15A comprising part of a nonvolatile semiconductor memory device having a floating gate are connected in series, a drain of the memory cell transistor MT0A of this NAND string is connected to the bit line BL1 via a selection gate SG1A, and a source of the memory cell transistor MT15A is connected to a reference voltage line VGL via a selection gate SG2A.
The memory string A1 has a NAND string in which memory cell transistors MT0B to MT15B comprising a part of a nonvolatile semiconductor memory device having a floating gate are connected in series, the drain of the memory cell transistor MT0B of this NAND string is connected to the bit line BL2 via a selection gate SG1B, and the source of the memory cell transistor MT15B is connected to a reference voltage line VGL via a selection gate SG2B.
The gates of the selection gates SG1A and SG1B are commonly connected to a selection signal supply line SSL, and the gates of the selection gates SG2A and SG2B are commonly connected to a selection signal supply line GSL.
A write/read control circuit 2 is constituted by n-channel MOS (NMOS) transistors NT1 to NT19, a p-channel MOS (PMOS) transistor PT1, and latch circuits Q1 and Q2 formed by connecting an input and an output of the inverter.
The NMOS transistor NT1 is connected between a supply line of a power supply voltage V.sub.cc and the bit line BL1, and the gate is connected to the supply line of an inhibit signal IHB1. The NMOS transistor NT2 is connected between the supply line of the power supply voltage V.sub.cc and the bit line BL2, and the gate is connected to the supply line of an inhibit signal IHB2.
A depletion type NMOS transistor NT18 is connected between a connection point of the NMOS transistor NT3 and the NMOS transistor NT1 and the connection point of the memory string A0 and the bit line BL1, and a depletion type NMOS transistor NT19 is connected between the connection point of the NMOS transistor NT4 and the NMOS transistor NT2 and the connection point of the memory string A1 and the bit line BL2. The gates of the NMOS transistors NT18 and NT19 are connected to a decouple signal supply line DCPL.
The NMOS transistors NT3, NT5, and NT16 are connected in series between the connection point of the depletion type NMOS transistor NT18 and the NMOS transistor NT1 and a bus line IOi, and the NMOS transistors NT4, NT7 and NT17 are connected in series between the connection point of the depletion type NMOS transistor NT19 and the NMOS transistor NT2 and a bus line IOi+1.
Further, the connection point of the NMOS transistors NT3 and NT5 and the connection point of the NMOS transistors NT4 and NT7 are grounded via the NMOS transistor NT6 and, connected to the drain of the PMOS transistor PT1 and the gates of the NMOS transistors NT8 and NT13. The gate of the NMOS transistor NT6 is connected to the supply line of a reset signal RST, the source of the PMOS transistor PT1 is connected to the supply line of the power supply voltage V.sub.cc, and the gate of the PMOS transistor PT1 is connected to the supply line of the signal Vref.
A first storage node N1a of the latch circuit Q1 is connected to the connection point of the NMOS transistors NT5 and NT16, and a second storage node N1b is grounded via NMOS transistors NT8 to NT10 connected in series.
A first storage node N2a of the latch circuit Q2 is connected to the connection point of the NMOS transistors NT7 and NT17, and a second storage node N2b is grounded via NMOS transistors NT13 to NT15 connected in series.
Further, the connection point of the NMOS transistors NT8 and NT9 is grounded via NMOS transistors NT11 and NT12 connected in series.
The gate of the NMOS transistor NT9 is connected to the first storage node N2a of the latch circuit Q2, the gate of the NMOS transistor NT10 is connected to the supply line of a signal .O slashed.LAT2, the gate of the NMOS transistor NT11 is connected to the second storage node N2b, the gate of the NMOS transistor NT12 is connected to the supply line of a signal .O slashed.LAT1, and gates of the NMOS transistors NT14 and NT15 are connected to the supply line of a signal .O slashed.LAT3.
The gate of the NMOS transistor NT16 serving as a column gate is connected to the supply line of a signal Yi, and the gate of the NMOS transistor NT17 serving as a column gate is connected to the supply line of a signal Yi+1.
Further, FIG. 3A is a timing chart at the time of reading; and FIG. 3B is a timing chart at the time of a write operation (programming).
As seen from FIG. 3B, the write operation of 4 values is carried out in three steps. The operation routine shifts to a next step at a stage where it is decided that all cells for which a write operation originally was to be performed in units of pages in each step are sufficiently written.
An explanation will be made of the read operation next.
First, the reset signal RST and signals PGM1 and PGM2 are set to the high level. By this, the first storage nodes N1a and N2a of the latch circuits Q1 and Q2 are pulled to the ground level. As a result, the latch circuits Q1 and Q2 are cleared.
Next, the read operation is carried out by setting the word line voltage to 2.4 V. Due to a fact that the cell current does not flow if the threshold voltage Vth is higher than the word line voltage (2.4 V), the bit line voltage holds the precharge voltage and its high level is sensed. On the other hand, due to the fact that the cell current flows if the threshold voltage Vth is lower than the word line voltage (2.4 V), the bit line voltage falls and its low level is sensed.
Next, the read operation is carried out at the word line voltage of 1.2 V. Finally the read operation is carried out at the word line voltage of 0 V.
More specifically, when the cell data is "00", the current does not flow in any of the word lines, therefore (1, 1) is output to the buses IOi+1 and IOi. First, when reading the data by setting the word line voltage at 2.4 V, the control signal .O slashed.LAT1 is set to a high level. At this time, the bit line is held at the high level since the cell current does not flow, so the NMOS transistor NT8 is held in the conductive state, and the second storage node N2b of the latch circuit Q2 is held at the high level since the latch circuit Q2 is cleared, so the NMOS transistor NT11 is held in the conductive state. Accordingly, the NMOS transistors NT8, NT11, and NT12 are held in the conductive state, the second storage node N1b of the latch circuit Q1 is pulled to the ground level, and the first storage node N1a of the latch circuit Q1 shifts to the high level. Next, when reading the data by setting the word line to 1.2 V, the control signal .O slashed.LAT3 is set to the high level. At this time, the bit line is held at the high level since the cell current does not flow, so the NMOS transistor NT13 is held in the conductive state, the second storage node N2b of the latch circuit Q2 is pulled to the ground level, and the first storage node N2a of the latch circuit Q2 shifts to the high level. Finally, when reading the data by setting the word line to 0 V, the control signal .O slashed.LAT1 is set to a high level. At this time, the bit line is held at the high level since the cell current does not flow, so the NMOS transistor NT8 is held in the conductive state, but the NMOS transistor NT11 becomes a non-conductive state since the second storage node N2b of the latch circuit Q2 is at the low level, and the first storage node N1a of the latch circuit Q1 holds the high level.
When the cell data is "01", the current flows only in the case of the word line voltage VWL00, and (0, 1) is output to the buses IOi+1 and IOi. First, when reading the data by setting the word line voltage to 2.4 V, the control signal .O slashed.LAT1 is set to a high level. At this time, the bit line becomes the low level since the cell current flows, so the NMOS transistor NT8 is held in the non-conductive state and the first storage node N1a of the latch circuit Q1 holds the low level. Next, when reading the data by setting the word line to 1.2 V, the control signal .O slashed.LAT3 is set to the high level. At this time, the bit line is held at the high level since the cell current does not flow, so the NMOS transistor NT13 is held in the conductive state, the second storage node N2b of the latch circuit Q2 is pulled to the ground level, and the first storage node N2a of the latch circuit Q2 shifts to the high level. Finally, when reading the data by setting the word line at 0 V, the control signal .O slashed.LAT1 is set to the high level. At this time, the bit line is held at the high level since the cell current does not flow, so the NMOS transistor NT8 is held in the conductive state, but the NMOS transistor NT11 becomes a non-conductive state since the second storage node N2b of the latch circuit Q2 is at the low level, and the first storage node N1a of the latch circuit Q1 holds the low level.
In cases where the cell data are "10" and "11" as well, similarly (0, 1) and (0, 0) are read out to the buses IOi+1 and IOi.
Next, an explanation will be made of the write operation.
In the circuit of FIG. 2, first, the write operation is carried out by the data stored in the latch circuit Q1, next, the write operation is carried out by the data of the latch circuit Q2, and finally the write operation is carried out by the data of the latch circuit Q1 again.
Here, when the write data is (Q2, Q1)=(1, 0), if the latch circuit Q1 is sufficiently written, the data is inverted from "0" to "1", but when (Q2, Q1)=(0, 0), the latch circuit Q1 does not (cannot) invert the data from "0" to "1" even if sufficiently written in the first step since it is necessary to use this data also as the write data of a third step.
The end of the write operation in each step is judged in a stage where the latch data on the noted side (Q2 or Q1) becomes all "1".
In the cell where the write data (Q2, Q1)=(0, 0), there is no inversion by the latch circuit Q1 at the first step, so there is no judgement of an end by a wired OR.
In the circuit mentioned above, as shown in FIG. 4, first, after performing the write operation of the cell with the write data "10" and "00" (Step 1) in accordance with the data of the latch circuit Q1, the write operation of the cell with the write data "01" and "00" (Step2) is carried out in accordance with the data of the latch circuit Q2, and finally the write operation of the cell with the write data "00" (Step 3) is carried out.
Namely, in the circuit of the related art explained above, the write operation with the write data "10" and "01" is carried out in only Step 1 and Step 2, therefore the time for writing "10" and "01" corresponds to the write time of Step 1 and Step 2 as it is. The write operation of the cell with the write data "00" is carried out in all of Step 1 to Step 3, but the write operation of Step 3 is carried out after lowering the ISPP voltage in preparation for excess writing between Step 2 and Step 3.
From this, it may be deduced that the write time of a cell with the write data "00" is almost the same as the write time of Step 3. From this, the write operation is serially carried out. This becomes a cause of an increase of the write time for 4 values.
As seen from FIG. 4, the sum of write times for the data "10" and "01" is almost the same as the write time for the data "00".
Further, the write operation is carried out by using a self boost, but the write inhibit voltage charged in the bit line drops by the threshold voltage Vth by the NMOS transistor to which the signals PGM1 and PGM2 are supplied and has become Vcc-Vth(B) (Vth(B): Vth influenced by a back bias effect).
In order to make the self boost possible in this state, it is necessary to set the Vth of the selection gate of the drain side of the memory cell high. This becomes an obstacle in realizing an increase of speed of the read operation.
Further, bit lines are charged before writing by a latch. When viewed from the latch, however, a bit line is a huge capacitor having a voltage of 0 V, so there is a possibility of inversion of the latch data at the instant of contact with a bit line when the latch data is "1".
In order to avoid this, when charging a bit line in accordance with the write data, the charging is carried out while setting the gate voltage of the NMOS transistors NT5 and NT7 low. For this reason, the charge current becomes small, and a long time has been taken for the charging of the bit line.
Further, a long time is taken for a verify read operation.